ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
WAVEFORM SAMPLING MODE
The waveform samples of the current and voltage waveform,
the active, reactive, and apparent power outputs are stored every
125 µs (8 kHz rate) into 24-bit signed registers that can be
accessed through various serial ports of the ADE7854A/
ADE7858A/ADE7868A/ADE7878A. Table 21 provides a list
of registers and their descriptions.
Table 21. Waveform Registers List
Register
Description
IAWV
Phase A current
VAWV
Phase A voltage
IBWV
Phase B current
VBWV
Phase B voltage
ICWV
Phase C current
VCWV
Phase C voltage
INWV
Neutral current, available in the ADE7868A
and ADE7878A only
AVA
Phase A apparent power
BVA
Phase B apparent power
CVA
Phase C apparent power
AWATT
Phase A total active power
BWATT
Phase B total active power
CWATT
Phase C total active power
AVAR
Phase A total reactive power
BVAR
Phase B total reactive power
CVAR
Phase C total reactive power
Bit 17 (DREADY) in the STATUS0 register can be used to
signal when the registers listed in Table 21 can be read using
I2C or SPI serial ports. An interrupt attached to the flag can be
enabled by setting Bit 17 (DREADY) in the MASK0 register.
For more information about the DREADY bit, see the Digital
Signal Processor section.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A contain a
high speed data capture (HSDC) port that is specially designed
to provide fast access to the waveform sample registers (see the
HSDC Interface section). There is also an SPI burst mode
available to access all waveform registers with one command
(see the SPI Burst Read Operation section).
As stated in the Current Waveform Gain Registers section,
the serial ports of the ADE7854A/ADE7858A/ADE7868A/
ADE7878A work on 32-, 16-, or 8-bit words. All registers listed
in Table 21 are transmitted sign-extended from 24 bits to 32 bits
(see Figure 38).
ENERGY TO FREQUENCY CONVERSION
The ADE7854A/ADE7858A/ADE7868A/ADE7878A provide
three frequency output pins: CF1, CF2, and CF3/HSCLK. The
CF3 output is multiplexed with the serial clock output of the
HSDC interface. When HSDC is enabled, the CF3 functionality is
disabled at the pin. The CF1 and CF2 pins are always available.
Note that throughout this section, the CF3/HSCLK dual
function pin name is referenced by the relevant calibration
frequency output function only, CF3 (see the Pin Configuration
and Function Descriptions section for full pin mnemonics and
descriptions).
After initial calibration at manufacturing, the manufacturer or
end user verifies the energy meter calibration. One convenient
way to verify the meter calibration is to provide an output
frequency proportional to the active, reactive, or apparent
powers under steady load conditions. This output frequency
can provide a simple, single-wire, optically isolated interface to
external calibration equipment. Figure 78 illustrates the energy
to frequency conversion in the ADE7854A/ADE7858A/
ADE7868A/ADE7878A.
The DSP computes the instantaneous values of all phase powers:
total active, fundamental active, total reactive, fundamental
reactive, and apparent. The process in which the energy is sign
accumulated in various xWATTHR, xVARHR, and xVAHR
registers is described in the energy calculation sections: Active
Energy Calculation, Reactive Energy Calculation, and Apparent
Energy Calculation. In the energy to frequency conversion
process, the instantaneous powers generate signals at the
frequency output pins (CF1, CF2, and CF3/HSCLK). One
digital-to-frequency converter is used for every CFx pin. Every
converter sums certain phase powers and generates a signal that
is proportional to the sum. Two sets of bits determine which
powers are converted.
First, Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),
and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register
determine which phases, or which combination of phases, are
added.
The TERMSEL1 bits refer to the CF1 pin, the TERMSEL2 bits
refer to the CF2 pin, and the TERMSEL3 bits refer to the
CF3/HSCLK pin. The TERMSELx[0] bits manage Phase A.
When set to 1, Phase A power is included in the sum of powers
at the CFx converter. When cleared to 0, Phase A power is not
included. The TERMSELx[1] bits manage Phase B, and the
TERMSELx[2] bits manage Phase C. Setting all TERMSELx bits
to 1 means that all 3-phase powers are added at the CFx
converter. Clearing all TERMSELx bits to 0 means no phase
power is added and no CF pulse is generated.
Second, Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and
Bits[8:6] (CF3SEL[2:0]) in the CFMODE register decide what
type of power is used at the inputs of the CF1, CF2, and CF3
converters, respectively. Table 22 shows the values that CFxSEL
can have: total active, total reactive (available in the ADE7858A,
ADE7868A, and ADE7878A only), apparent, fundamental
active (available in the ADE7878A only), or fundamental
reactive (available in the ADE7878A only) powers.
Rev. C | Page 60 of 96
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