Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
ZXSEL[0] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE A)
ZXSEL[1] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE B)
ZXSEL[2] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE C)
LINECYC[15:0]
CALIBRATION
CONTROL
AVAROS
AVARGAIN
OUTPUT
FROM
TOTAL
REACTIVE
POWER
ALGORITHM
ACCUMUL ATOR
VARTHR[47:0]
AVARHR[31:0]
32-BIT
REGISTER
Figure 75. Line Cycle Total Reactive Energy Accumulation Mode
Phase A, Phase B, and Phase C zero crossings are included when
counting the number of half line cycles by setting Bits[5:3]
(ZXSEL[x]) in the LCYCMODE register. Any combination of
the zero crossings from all three phases can be used for
counting the zero crossing. Select only one phase at a time for
inclusion in the zero-crossings count during calibration.
For more information about setting the LINECYC register and
Bit 5 (LENERGY) in the MASK0 interrupt mask register associ-
ated with the line cycle accumulation mode, see the Line Cycle
Active Energy Accumulation Mode section.
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be
delivered to a load. One way to obtain the apparent power is by
multiplying the voltage rms value by the current rms value (the
arithmetic apparent power)
S = V rms × I rms
(48)
where:
S is the apparent power.
V rms and I rms are the rms voltage and current, respectively.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A compute
the arithmetic apparent power on each phase. Figure 76 illustrates
the signal processing in each phase for the calculation of the
apparent power in the ADE7854A/ADE7858A/ADE7868A/
ADE7878A. Because V rms and I rms contain all harmonic
information, the apparent power computed by the device is total
apparent power. Note that the ADE7878A does not compute
fundamental apparent power because it does not measure the rms
values of the fundamental voltages and currents.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A store the
instantaneous phase apparent powers in the AVA, BVA, and
CVA registers, expressed as
xVA
V
VFS
I
I FS
PMAX
1
24
(49)
where:
V, I are the rms values of the phase voltage and current,
respectively.
VFS, IFS are the rms values of the phase voltage and current when
the ADC inputs are at full scale.
PMAX = 33,516,139, which is the instantaneous power
computed when the ADC inputs are at full scale and in phase.
Note that the xVA[23:0] waveform registers are accessible
through various serial ports (see the Waveform Sampling Mode
section).
The ADE7854A/ADE7858A/ADE7868A/ADE7878A can
compute the apparent power in an alternative way by multiplying
the phase rms current by an rms voltage introduced externally
(see the Apparent Power Calculation Using VNOM section).
Apparent Power Gain Calibration
The average apparent power result in each phase can be scaled
by ±100% by writing to the respective xVAGAIN 24-bit register
(AVAGAIN, BVAGAIN, or CVAGAIN).
The xVAGAIN registers are twos complement, signed registers
and have a resolution of 2−23/LSB. The function of the
xVAGAIN registers is expressed mathematically as
Average Apparent Power
V rms I rms
1
xVAGAIN Register
223
(50)
where x represents the A, B, or C phase.
The output is scaled by −50% by writing 0xC00000 to the
xVAGAIN registers, and it is increased by +50% by writing
0x400000 to them. These registers calibrate the apparent power
(or energy) calculation in the ADE7854A/ADE7858A/
ADE7868A/ADE7878A for each phase.
As previously stated in the Current Waveform Gain Registers
section, the serial ports of the ADE7854A/ADE7858A/
ADE7868A/ADE7878A work on 32-, 16-, or 8-bit words and
the DSP works on 28 bits. Similar to the registers shown in
Figure 34, the AVAGAIN, BVAGAIN, and CVAGAIN 24-bit
registers are accessed as 32-bit registers with the four MSBs
padded with 0s and sign extended to 28 bits.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register
to calibrate and eliminate the dc component in the rms value
(see the Root Mean Square Measurement section). The voltage
and current rms values are multiplied together in the apparent
power signal processing. Because no additional offsets are created
in the multiplication of the rms values, there is no specific offset
compensation in the apparent power signal processing. The offset
compensation of the apparent power measurement in each phase is
accomplished by calibrating each individual rms measurement.
Rev. C | Page 57 of 96