Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADE7854AACPZ View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADE7854AACPZ
ADI
Analog Devices ADI
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
the corresponding bit set to 1 to clear the status bit and to set
the IRQ0 pin to high.
Reactive Energy Calculation
Reactive energy is defined as the integral of reactive power.
Reactive Energy = ∫q(t)dt
(44)
Both total and fundamental reactive energy accumulations are
always a signed operation. Negative energy is subtracted from
the reactive energy contents.
Similar to active power, the ADE7858A/ADE7868A/ADE7878A
achieve the integration of the reactive power signal in two stages
(see Figure 74). The process is identical for both total and
fundamental reactive powers.
The first stage is conducted inside the DSP: every 125 µs
(8 kHz frequency), the instantaneous phase total reactive
or fundamental power is accumulated into an internal
register. When a threshold is reached, a pulse is generated
at the processor port and the threshold is subtracted from
the internal register. The sign of the energy in this moment
is considered the sign of the reactive power (for more
information, see the Sign of Reactive Power Calculation
section).
The second stage is performed outside the DSP and consists
of accumulating the pulses generated by the processor into
internal 32-bit accumulation registers. The content of these
registers is transferred to the VAR-hour registers (xVARHR
and xFVARHR) when these registers are accessed.
AVARHR, BVARHR, CVARHR, AFWATTHR,
BFWATTHR, and CFWATTHR represent phase
fundamental reactive powers.
Figure 70 in the Active Energy Calculation section explains this
process. The VARTHR combined 48-bit signed register contains
the threshold introduced by the user; it is common for both total
and fundamental phase reactive powers. Its value depends on
how much energy is assigned to one LSB of var-hour registers.
When a derivative of reactive energy (varh) of [10n varh], where
n is an integer, is desired as one LSB of the xVARHR register;
then, the VARTHR register can be computed using the following
equation:
VARTHR = PMAX × fs × 3600 ×10n
VFS × I FS
(45)
where:
PMAX = 33,516,139 = 0x1FF6A6B, which is the instantaneous
power computed when the ADC inputs are at full scale.
fS = 8 kHz, the frequency with which the DSP computes the
instantaneous power.
VFS, IFS are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
The maximum value that may be written on the VARTHR
register is 247 − 1. The minimum value is 0x0; however, it is best
to write a number equal to or greater than PMAX. Never use
negative numbers.
Similar to the WTHR register (see Figure 72), VARTHR, a 48-bit
register, is accessed as two 32-bit registers (VARTHR1 and
VARTHR0), each having eight MSBs padded with 0s. As previously
stated in the Voltage Waveform Gain Registers section, the serial
ports of the ADE7858A/ADE7868A/ADE7878A work on 32-,
16-, or 8-bit words.
This discrete time accumulation or summation is equivalent to
integration in continuous time as shown in Equation 46.
Reactive Energy =
q(t)dt =
Lim
q(nT)
T 0 n= 0
×
T


(46)
where:
n is the discrete time sample number.
T is the sample period.
On the ADE7858A/ADE7868A/ADE7878A, the total phase
reactive powers accumulate in the AVARHR, BVARHR, and
CVARHR 32-bit signed registers. The fundamental phase reactive
powers accumulate in the AFVARHR, BFVARHR, and
CFVARHR 32-bit signed registers. The reactive energy register
content can roll over to full-scale negative (0x80000000) and
continue increasing in value when the reactive power is positive.
Conversely, when the reactive power is negative, the energy
register underflows to full-scale positive (0x7FFFFFFF) and
continues to decrease in value.
Bit 2 (REHF) in the STATUS0 register is set when Bit 30 of
one of the xVARHR registers changes, signifying one of these
registers is half full. When the reactive power is positive, the
var-hour register becomes half full when it increments from
0x3FFFFFFF to 0x40000000. When the reactive power is
negative, the var-hour register becomes half full when it decre-
ments from 0xC0000000 to 0xBFFFFFFF. Analogously, Bit 3
(FREHF) in the STATUS0 register is set when Bit 30 of one of the
xFVARHR registers changes, signifying that one of these
registers is half full.
Setting Bits[3:2] in the MASK0 register enable the FREHF and
REHF interrupts, respectively. When enabled, the IRQ0 pin is
set low and the status bit is set to 1 whenever one of the energy
registers, xVARHR (for REHF interrupt) or xFVARHR (for
FREHF interrupt), becomes half full. Writing to the STATUS0
register with the corresponding bit set to 1 clears the status bit
and sets the IRQ0 pin to high.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
read with reset for all var-hour accumulation registers, that is,
the registers are reset to 0 after a read operation.
Rev. C | Page 55 of 96
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]