ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
IA
APHCAL
VA
HPFDIS
[23:0]
HPF
HPFDIS
[23:0]
DIGITAL
INTEGRATOR AIGAIN
AVGAIN
AVARGAIN
AVAROS
TOTAL
REACTIVE
POWER
ALGORITHM
HPF
ACCUMULATOR
VARTHR[47:0]
AVAR
DIGITAL SIGNAL PROCESSOR
24
Figure 74. Total Reactive Energy Accumulation
REVRPA BIT IN
STATUS0[31:0]
AVARHR[31:0]
32-BIT
REGISTER
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation register is
125 μs (8 kHz frequency). With full-scale pure sinusoidal signals
on the analog inputs and a 90° phase difference between the
voltage and the current signal (the largest possible reactive
power), the average word value representing the reactive power is
PMAX = 33,516,139 = 0x1FF6A6B. Setting the VARTHR
threshold at the PMAX level means that the DSP generates a
pulse that is added at the var-hour registers every 125 μs.
The maximum value that can be stored in the var-hour accu-
mulation register before it overflows is 231 − 1 or 0x7FFFFFFF.
The integration time is calculated as
Time = 0x7FFFFFFF × 125 μs = 74 hr, 33 min, 55 sec (47)
Energy Accumulation Modes
The reactive power accumulated in each var-hour accumulation
32-bit register (AVARHR, BVARHR, CVARHR, AFVARHR,
BFVARHR, and CFVARHR) depends on the configuration of
Bits[5:4] (CONSEL[1:0]) in the ACCMODE register, in correlation
with the watt-hour registers. The different configurations are
listed in Table 19. Note that IAʹ/IBʹ/ICʹ are the phase shifted
current waveforms.
Table 19. Inputs to Var-Hour Accumulation Registers
AVARHR,
CONSEL[1:0] AFVARHR
BVARHR,
BFVARHR
CVARHR,
CFVARHR
00
VA × IA’
VB × IB’
VC × IC’
01
VA × IA’
VB × IB’
VC × IC’
VB = VA − VC1
10
VA × IA’
VB × IB’
VC × IC’
VB = −VA − VC
11
VA × IA’
VB × IB’
VC × IC’
VB = −VA
Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine
how the CFx frequency output can be a generated function of the
total and fundamental reactive powers. Whereas the var-hour
accumulation registers accumulate the reactive power in a signed
format, the frequency output can be generated in either the signed
mode, the sign adjusted mode, or the absolute mode by setting the
appropriate bits in VARACC[1:0]. See the Energy to Frequency
Conversion section for more information.
Line Cycle Reactive Energy Accumulation Mode
In line cycle energy accumulation mode (see the Line Cycle
Active Energy Accumulation Mode section), the energy accu-
mulation can be synchronized to the voltage channel zero
crossings to accumulate reactive energy over an integral
number of half line cycles.
In this mode, the ADE7858A/ADE7868A/ADE7878A transfer
the reactive energy accumulated in the 32-bit internal accumula-
tion registers into the xVARHR or xFVARHR registers after an
integral number of line cycles, as shown in Figure 75. The
LINECYC register specifies the number of half line cycles.
Setting Bit 1 (LVAR) in the LCYCMODE register activates the
line cycle reactive energy accumulation mode. The total reactive
energy accumulated over an integer number of half line cycles
or zero crossings is available in the var-hour accumulation registers
after the number of zero crossings specified in the LINECYC
register is detected. When using the line cycle accumulation
mode, set Bit 6 (RSTREAD) of the LCYCMODE register to
Logic 0 because a read with a reset of var-hour registers is not
available in this mode.
1 In a 3-phase, 3-wire case (CONSEL[1:0] = 01), the device computes the rms
value of the line voltage between Phase A and Phase C and stores the result
into BVRMS register (see the Voltage RMS in 3-Phase, 3-Wire Delta Configurations
section). Consequently, the device computes powers associated with Phase
B that do not have physical meaning. To avoid any errors in the frequency
output pins (CF1, CF2, or CF3/HSCLK) related to the powers associated with
Phase B, disable the contribution of Phase B to the energy to frequency
converters by setting Bit TERMSEL1[1], Bit TERMSEL2[1], or Bit TERMSEL3[1]
to 0 in the COMPMODE register (see the Energy to Frequency Conversion
section).
Rev. C | Page 56 of 96
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