ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
Table 15. Inputs to Watt-Hour Accumulation Registers
CONSEL AWATTHR BWATTHR
CWATTHR
00
VA × IA
VB × IB
VC × IC
01
VA × IA
VB × IB
VC × IC
VB = VA − VC1
10
VA × IA
VB × IB
VC × IC
VB = −VA − VC
11
VA × IA
VB × IB
VC × IC
VB = −VA
1 In a 3-phase, 3-wire case (CONSEL[1:0] = 01), the device computes the rms
value of the line voltage between Phase A and Phase C and stores the result
in the BVRMS register (see the Voltage RMS in 3-Phase, 3-Wire Delta
Configurations section). Consequently, the device computes powers
associated with Phase B that do not have physical meaning. To avoid any
errors in the frequency output pins (CF1, CF2, or CF3/HSCLK) related to the
powers associated with Phase B, disable the contribution of Phase B to the
energy-to-frequency converters by setting Bit TERMSEL1[1], Bit TERMSEL2[1], or
Bit TERMSEL3[1] to 0 in the COMPMODE register (see the Energy to
Frequency Conversion section).
Depending on the polyphase meter service, choose the appro-
priate formula to calculate the active energy. The American
ANSI C12.10 standard defines the different configurations of
the meter. Table 16 lists which mode to choose in these various
configurations.
Table 16. Meter Form Configuration
ANSI Meter Form Configuration
5S/13S
3-wire delta
6S/14S
4-wire wye
8S/15S
4-wire delta
9S/16S
4-wire wye
CONSEL[1:0]
01
10
11
00
Bits[1:0] (WATTACC[1:0]) in the ACCMODE register determines
how the CF frequency output can be generated as a function of
the total and fundamental active powers. Whereas the watt-hour
accumulation registers accumulate the active power in a signed
format, the frequency output can be generated in either signed
mode or absolute mode as a function of the WATTACC[1:0]
bits. See the Energy to Frequency Conversion section for more
information.
Line Cycle Active Energy Accumulation Mode
In line cycle active energy accumulation mode, the energy
accumulation synchronizes to the voltage channel zero
crossings such that active energy accumulates over an integral
number of half line cycles. The advantage of summing the
active energy over an integer number of line cycles is that the
sinusoidal component in the active energy is reduced to 0. This
eliminates any ripple in the energy calculation and allows the
energy to accumulate accurately over a shorter time. Using the
line cycle energy accumulation mode greatly simplifies energy
calibration and significantly reduces meter calibration time.
In line cycle energy accumulation mode, the ADE7854A/
ADE7858A/ADE7868A/ADE7878A transfer the active energy
accumulated in the 32-bit internal accumulation registers into the
xWATTHR or xFWATTHR registers after an integral number of
line cycles, as shown in Figure 73. The LINECYC register
specifies the number of half line cycles.
ZXSEL[0] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE A)
ZXSEL[1] IN
LCYCMODE[7:0]
LINECYC[15:0]
ZERO-
CROSSING
DETECTION
(PHASE B)
ZXSEL[2] IN
LCYCMODE[7:0]
CALIBRATION
CONTROL
ZERO-
CROSSING
DETECTION
(PHASE C)
AWATTOS
AWGAIN
OUTPUT
FROM LPF2
ACCUMUL ATOR
WTHR[47:0]
AWATTHR[31:0]
32-BIT
REGISTER
Figure 73. Line Cycle Active Energy Accumulation Mode
Setting Bit 0 (LWATT) in the LCYCMODE register activates the
line cycle active energy accumulation mode. After LINECYC
detects the number of half line cycles, the energy accumulation
over an integer number of half line cycles is written to the watt-
hour accumulation registers. When using the line cycle
accumulation mode, set Bit 6 (RSTREAD) of the LCYCMODE
to Logic 0 because the read with reset of watt-hour registers is
not available in this mode.
Phase A, Phase B, and Phase C zero crossings are included
when counting the number of half line cycles by setting Bits[5:3]
(ZXSEL[x]) in the LCYCMODE register. Any combination of
the zero crossings from all three phases can be used for
counting the zero crossing. Select only one phase at a time for
inclusion in the zero-crossing count during calibration.
The LINECYC 16-bit unsigned register specifies the number
of zero crossings. The ADE7854A/ADE7858A/ADE7868A/
ADE7878A can accumulate active power for up to 65,535
combined zero crossings. Note that the internal zero-crossing
counter is always active. By setting Bit 0 (LWATT) in the
LCYCMODE register, the first energy accumulation result is,
therefore, incorrect. Writing to the LINECYC register when the
LWATT bit is set resets the zero-crossing counter, thus ensuring
that the first energy accumulation result is accurate.
At the end of an energy calibration cycle, Bit 5 (LENERGY) in
the STATUS0 register is set. If the corresponding mask bit in
the MASK0 interrupt mask register is enabled, the IRQ0 pin
goes active low. Writing to the STATUS0 register with the
corresponding bit set to 1 clears the status bit and resets the
IRQ0 pin to high. Because the active power is integrated on an
integer number of half line cycles in this mode, the sinusoidal
Rev. C | Page 52 of 96
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