Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADE7854AACPZ View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADE7854AACPZ
ADI
Analog Devices ADI
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Bit 4 (VAEHF) in the STATUS0 register is set when Bit 30 of one of
the xVAHR registers changes, signifying one of these registers is
half full. Because the apparent power is always positive and the
xVAHR registers are signed, the VA-hour registers become half full
when they increment from 0x3FFFFFFF to 0x40000000. Enable
interrupts that are attached to Bit VAEHF in the STATUS0 register
by setting Bit 4 in the MASK0 register. Enabling sets the IRQ0 pin
to low and sets the status bit to 1 whenever one of the Energy
Registers xVAHR becomes half full. Writing to the STATUS0
register with the corresponding bit set to 1 clears the status bit
and sets the IRQ0 pin to high.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables
a read-with-reset for all xVAHR accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period for the accumulation register is
125 μs (8 kHz frequency). With full-scale pure sinusoidal signals
on the analog inputs, the average word value representing the
apparent power is PMAX. Setting the VATHR threshold register at
the PMAX level means that the DSP generates a pulse that is
added at the xVAHR registers every 125 μs.
The maximum value that can be stored in the xVAHR accumu-
lation register before it overflows is 231 − 1 or 0x7FFFFFFF.
Calculate the integration time as
Time = 0x7FFFFFFF × 125 μs = 74 hr, 33 min, 55 sec (55)
Energy Accumulation Mode
The amount of apparent power that accumulates in each
accumulation register depends on the configuration of Bits[5:4]
(CONSEL[1:0]) in the ACCMODE register. See Table 20 for the
various configurations of inputs to the VA-hour accumulation
registers.
Table 20. Inputs to VA-Hour Accumulation Registers
CONSEL[1:0] AVAHR
BVAHR
CVAHR
00
VA rms × IA rms VB rms × IB rms VC rms × IC rms
01
VA rms × IA rms VB rms × IB rms VC rms × IC rms
VB = VA − VC1
10
VA rms × IA rms VB rms × IB rms VC rms × IC rms
VB = −VA − VC
11
VA rms × IA rms VB rms × IB rms VC rms × IC rms
VB = − VA
1 In a 3-phase, 3-wire case (CONSEL[1:0] = 01), the device computes the rms
value of the line voltage between Phase A and Phase C and stores the result
in the BVRMS register (see the Voltage RMS in 3-Phase, 3-Wire Delta
Configurations section). Consequently, the device computes powers
associated with Phase B that do not have physical meaning. To avoid any
errors in the frequency output pins (CF1, CF2, or CF3/HSCLK) related to the
powers associated with Phase B, disable the contribution of Phase B to the
energy to frequency converters by setting Bit TERMSEL1[1], Bit TERMSEL2[1],
or Bit TERMSEL3[1] to 0 in the COMPMODE register (see the Energy to
Frequency Conversion section).
Line Cycle Apparent Energy Accumulation Mode
In line cycle energy accumulation mode, it is possible to
synchronize the energy accumulation to the voltage channel
zero crossings, allowing apparent energy to be accumulated
over an integral number of half line cycles (see the Line Cycle
Active Energy Accumulation Mode section). In this mode, the
ADE7854A/ADE7858A/ADE7868A/ADE7878A transfer the
apparent energy accumulated in the 32-bit internal accumula-
tion registers into the xVAHR registers after an integral number
of line cycles, as shown in Figure 77. The LINECYC register
specifies the number of half line cycles.
ZXSEL[0] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE A)
ZXSEL[1] IN
LCYCMODE[7:0]
LINECYC[15:0]
ZERO-
CROSSING
DETECTION
(PHASE B)
CALIBRATION
CONTROL
ZXSEL[2] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE C)
AIRMS
AVAGAIN
AVAHR[31:0]
AVRMS
ACCUMUL ATOR
VAHR[47:0]
32-BIT
REGISTER
Figure 77. Line Cycle Apparent Energy Accumulation Mode
The line cycle apparent energy accumulation mode is activated
by setting Bit 2 (LVA) in the LCYCMODE register. The apparent
energy accumulated over an integer number of zero crossings is
written to the xVAHR accumulation registers after the number
of zero crossings specified in LINECYC register is detected. When
using the line cycle accumulation mode, set Bit 6 (RSTREAD) of
the LCYCMODE register to Logic 0 because a read with the reset
of xVAHR registers is not available in this mode.
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-
nation of the zero crossings from all three phases can be used
for counting the zero crossing. Select only one phase at a time
for inclusion in the zero-crossings count during calibration.
For more information about setting the LINECYC register and
Bit 5 (LENERGY) in the MASK0 interrupt mask register
associated with the line cycle accumulation mode, see the Line
Cycle Active Energy Accumulation Mode section.
Rev. C | Page 59 of 96
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]