Required Timing between Read and
Write Commands (tsxx)
There are minimum timing
requirements between read and
write commands on the serial
port.
SCK
Address
Data
Write Operation
Figure 25. Timing between two write commands.
t SWW
≥100 µs
Address
Data
Write Operation
If the rising edge of the SCK for 100 microsecond required delay,
the last data bit of the second
then the first write command
write command occurs before the may not complete correctly.
SCK
Address
Data
Write Operation
Figure 26. Timing between write and read commands.
t SWR
≥100 µs
Address
Next Read
Operation
If the rising edge of SCK for the
last address bit of the read
command occurs before the
100 microsecond required delay,
then the write command may not
complete correctly.
t1
≥100 µs
tSRW and tSRR
>250 ns
SCK
Address
Data
Address
Read Operation
Figure 27. Timing between read and either write or subsequent read commands.
Next Read or
Write Operation
The falling edge of SCK for the
first address bit of either the
read or write command must be
at least 250 ns after the last SCK
rising edge of the last data bit of
the previous read operation.
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