ADNS-2610 View Datasheet(PDF) - Agilent Technologies, Inc
Part Name
Description
MFG CO.
'ADNS-2610' PDF : 27 Pages View PDF
Serial Port Timer Timeout
VDD
>t SPTT
SCK
SDIO
Address = 0x01
Figure 29. Power-up serial port timer sequence.
Data = 0x0b000XXXXX
Don't Care State
If the microprocessor waits at
least tSPTT from VDD valid, it will
ensure that the ADNS-2610 has
powered up and the timer has
timed out. This assumes that the
microprocessor and the
ADNS-2610 share the same power
supply. If not, then the micropro-
cessor must wait for tSPTT from
ADNS-2610 VDD valid. Then when
the SCK toggles for the address,
the ADNS-2610 will be in sync
with the microprocessor.
Resync Note
If the microprocessor and the
ADNS-2610 get out of sync, then
the data either written or read
from the registers will be incor-
rect. An easy way to solve this is
to use watchdog timer timeout
sequence to resync the parts
after an incorrect read.
Power-up
ADNS-2610 has an on-chip
internal power-up reset (POR)
circuit, which will reset the chip
when VDD reaches the valid
value for the chip to function.
Soft Reset
ADNS-2610 may also be given the
reset command at any time via
the serial I/O port. The timing
and transactions are the same as
those just specified for the
power-up mode in the previous
section.
The proper way to perform soft
reset on ADNS-2610 is:
1. The microcontroller starts the
transaction by sending a write
operation containing the
address of the configuration
register and the data value of
0x80. Since the reset bit is set,
ADNS-2610 will reset and any
other bits written into the
configuration register at this
time is properly written into the
Configuration Register. After the
chip has been reset, very
quickly, the ADNS-2610 will
clear the reset bit so there is no
need for the microcontroller to
re-write the Configuration
Register to reset it.
2. The digital section is now ready
to go. It takes 3 frames for the
analog section to settle.
CLK
SCK
Reset Occurs
here
SDIO
1 A6 A5 A4 A3
Figure 30. ADNS-2610 soft reset sequence timing.
Soft reset will occur when
writing 0x80 to the configuration
register.
D5 D4 D3 D2 D1 D0
SCK
Write
Operation
1
0
Configuration Register Address
0
0
00
0
01
SDIO
Figure 31. Soft reset configuration register writing operation.
17
Configuration Register Data
0
00
00
00
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