ADP2108 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADP2108' PDF : 16 Pages View PDF
ADP2108
Data Sheet
12
10
8
6
4
2
0
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
Figure 30. Typical Capacitor Performance
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
( ) VRIPPLE
=
8×
I RIPPLE
fSW × COUT
≈
VIN
2π × fSW 2 × L ×COUT
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
ESRCOUT
≤
VRIPPLE
I RIPPLE
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is 7 µF.
Table 7. Suggested 10 μF Capacitors
Vendor
Murata
Taiyo Yuden
TDK
Type
X5R
X5R
X5R
Model
GRM188R60J106
JMK107BJ106
C1608JB0J106K
Case
Size
0603
0603
0603
Voltage
Rating (V)
6.3
6.3
6.3
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
ICIN ≥ I LOAD(MAX)
VOUT (VIN − VOUT )
VIN
To minimize supply noise, place the input capacitor as close to
the VIN pin of the ADP2108 as possible. As with the output
capacitor, a low ESR capacitor is recommended. The list of
recommended capacitors is shown in Table 8.
Table 8. Suggested 4.7 μF Capacitors
Vendor
Murata
Taiyo Yuden
TDK
Type
X5R
X5R
X5R
Model
GRM188R60J475
JMK107BJ475
C1608X5R0J475
Case
Size
0603
0603
0603
Voltage
Rating (V)
6.3
6.3
6.3
THERMAL CONSIDERATIONS
Because of the high efficiency of the ADP2108, only a small
amount of power is dissipated inside the ADP2108 package,
which reduces thermal constraints.
However, in applications with maximum loads at high ambient
temperature, low supply voltage, and high duty cycle, the heat
dissipated in the package is great enough that it may cause the
junction temperature of the die to exceed the maximum
junction temperature of 125°C. If the junction temperature
exceeds 150°C, the converter goes into thermal shutdown. It
recovers when the junction temperature falls below 130°C.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to power dissipation, as shown in the following
equation:
TJ = TA + TR
where:
TJ is the junction temperature.
TA is the ambient temperature.
TR is the rise in temperature of the package due to power
dissipation.
The rise in temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
TR = θJA × PD
where:
TR is the rise in temperature of the package.
θJA is the thermal resistance from the junction of the die to the
ambient temperature of the package.
PD is the power dissipation in the package.
PCB LAYOUT GUIDELINES
Poor layout can affect ADP2108 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following rules:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with several vias connecting to the com-
ponent side ground to further reduce noise interference on
sensitive circuit nodes.
Rev. H | Page 14 of 20
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