ADP2108
OUTLINE DIMENSIONS
1.060
1.020
0.980
2
1
BALL A1
IDENTIFIER
A
1.490
1.450
1.410
0.50
0.866 BSC
REF
B
C
0.657
0.602
0.546
TOP VIEW
(BALL SIDE DOWN)
SIDE VIEW
0.355
0.330
0.304
0.50 BSC
BOTTOM VIEW
(BALL SIDE UP)
COPLANARITY
0.04
SEATING
PLANE
0.330
0.310
0.290
0.280
0.250
0.220
Figure 36. 5-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-5-3)
Dimensions shown in millimeters
2.90 BSC
1.60 BSC
5
4
1
2
3
2.80 BSC
*0.90 MAX
0.70 MIN
1.90
BSC
0.95 BSC
*1.00 MAX 0.20
0.08
0.10 MAX
0.50
0.30
8°
SEATING
4°
0.60
PLANE
0°
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 37. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
Data Sheet
Rev. H | Page 16 of 20