ADSP-21061 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21061' PDF : 47 Pages View PDF
ADSP-21061/ADSP-21061L
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
Parameter
Supply Voltage (VDD)
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Lead Temperature (5 seconds)
Junction Temperature Under Bias
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
PACKAGE MARKING INFORMATION
The information presented in Figure 8 provides details about
the package branding for the ADSP-21061 processor. For a
complete listing of product availability, see Ordering Guide on
Page 52.
a
ADSP-21061
tppZccc
vvvvvv.x n.n
yyww country_of_origin
S
Figure 8. Typical Package Marking (Actual Marking Format May Vary)
Table 6. Package Brand Information
Brand Key
t
pp
Z
ccc
vvvvvv.x
n.n
yyww
Field Description
Temperature Range
Package Type
Lead Free Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
5V
–0.3 V to +7.0 V
–0.5 V to VDD +0.5 V
–0.5 V to VDD +0.5 V
200 pF
–65C to +150C
280ï‚°C
130ï‚°C
3.3 V
–0.3 V to +4.6 V
–0.5 V to VDD +0.5 V
–0.5 V to VDD +0.5 V
200 pF
–65C to +150C
280ï‚°C
130ï‚°C
TIMING SPECIFICATIONS
The timing specifications shown are based on a CLKIN fre-
quency of 50 MHz (tCK = 20 ns). The DT derating enables the
calculation of timing specifications within the min to max range
of the tCK specification (see Table 7). DT is the difference
between the derated CLKIN period (tCK) and a CLKIN period of
25 ns:
DT = tCK – 20 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive longer times.
For voltage reference levels, see Figure 29 under Test
Conditions.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices. (O/D) = Open Drain,
(A/D) = Active Drive.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Rev. D | Page 20 of 52 | May 2013
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