ADSP-21160M View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21160M' PDF : 52 Pages View PDF
ADSP-21160M/ADSP-21160N
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without reference
to CLKIN except for the ACK pin requirements listed in note 6
of Table 18. These specifications apply when the ADSP-21160x
is the bus master accessing external memory space in asynchro-
nous access mode.
Table 18. Memory Read—Bus Master
Parameter
Timing Requirements
tDAD
tDRLD
tHDA
tSDS
tHDRH
tDAAK
tDSAK
tSAKC
tHAKC
Address, CIF, Selects Delay to Data Valid1, 2, 3, 4
RDx Low to Data Valid1, 4, 5
Data Hold from Address, Selects6
Data Setup to RDx High1
Data Hold from RDx High6
ACK Delay from Address, Selects2, 7
ACK Delay from RDx Low7
ACK Setup to CLKIN7
ACK Hold After CLKIN
Min
0
8
1
0.5tCCLK + 3
1
Max
tCK – 0.25tCCLK – 8.5 + W
tCK – 0.5tCCLK + W
tCK – 0.5tCCLK – 12+ W
tCK – 0.75tCCLK – 11 + W
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
tDRHA
Address, CIF, Selects Hold After RDx High
0.25tCCLK – 1 + H
ns
tDARL
Address, CIF, Selects to RDx Low2
0.25tCCLK – 3
ns
tRW
RDx Pulsewidth
tCK – 0.5tCCLK – 1 + W
ns
tRWR
RDx High to WRx, RDx, DMAGx Low
0.5tCCLK – 1 + HI
ns
W = (number of wait states specified in WAIT register) ď‚´ tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1 Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.
2 The falling edge of MSx, BMS is referenced.
3 For ADSP-21160M, specification is tCK–0.25tCCLK–11+W ns, maximum.
4 The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high.
5 For ADSP-21160M, specification is 0.75tCK–11+W ns, maximum.
6 Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on page 49 for the calculation of hold times given capacitive
and dc loads.
7 For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,
ACK must be driven low (deasserted) by tDAAK, tDSAK, or tSAKC. For the second and subsequent cycles of an asynchronous external memory access, the tSAKC and tHAKC must be
met for both assertion and deassertion of ACK signal.
Rev. C | Page 26 of 60 | February 2013
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