ADSP-21160M View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21160M' PDF : 52 Pages View PDF
ADSP-21160M/ADSP-21160N
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without reference
to CLKIN except for the ACK pin requirements listed in note 1
of Table 19. These specifications apply when the ADSP-21160x
is the bus master accessing external memory space in asynchro-
nous access mode.
Table 19. Memory Write—Bus Master
Parameter
Timing Requirements
tDAAK
tDSAK
tSAKC
tHAKC
ACK Delay from Address, Selects1, 2
ACK Delay from WRx Low1
ACK Setup to CLKIN1
ACK Hold After CLKIN1
Min
0.5tCCLK + 3
1
Max
tCK – 0.5tCCLK– 12 + W
tCK – 0.75tCCLK – 11+ W
Unit
ns
ns
ns
ns
Switching Characteristics
tDAWH
Address, CIF, Selects to WRx Deasserted2
tCK – 0.25tCCLK – 3+ W
ns
tDAWL
Address, CIF, Selects to WRx Low2
0.25tCCLK – 3
ns
tWW
WRx Pulsewidth
tCK – 0.5tCCLK – 1 + W
ns
tDDWH
Data Setup before WRx High3
tCK – 0.5tCCLK – 1 + W
ns
tDWHA
Address Hold after WRx Deasserted
0.25tCCLK – 1 + H
ns
tDWHD
tDATRWH
Data Hold after WRx Deasserted
Data Disable after WRx Deasserted4
0.25tCCLK – 1 + H
0.25tCCLK – 2 + H
ns
0.25tCCLK+ 2 + H
ns
tWWR
WRx High to WRx, RDx, DMAGx Low
0.5tCCLK – 1+ HI
ns
tDDWR
Data Disable before WRx or RDx Low
0.25tCCLK – 1 + I
ns
tWDE
WRx Low to Data Enabled
–0.25tCCLK – 1
ns
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1 For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory
access, ACK must be driven low (deasserted) by tDAAK or tDSAK or tSAKC. For the second and subsequent cycles of an asynchronous external memory access, the tSAKC and
tHAKC must be met for both assertion and deassertion of ACK signal.
2 The falling edge of MSx, BMS is referenced.
3 For ADSP-21160M, specification is tCK–0.25tCCLK–12.5+W ns, minimum.
4 See Example System Hold Time Calculation on Page 49 for calculation of hold times given capacitive and dc loads.
Rev. C | Page 28 of 60 | February 2013
Share Link: 
