Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADSP-21160M View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADSP-21160M
ADI
Analog Devices ADI
'ADSP-21160M' PDF : 58 Pages View PDF
ADSP-21160M/ADSP-21160N
DMA Handshake
See Table 26 and Figure 23. These specifications describe the
three DMA handshake modes. In all three modes, DMARx is
used to initiate transfers. For handshake mode, DMAGx con-
trols the latching or enabling of data externally. For external
handshake mode, the data transfer is controlled by the
ADDR31–0, RDx, WRx, PAGE, MS3–0, ACK, and DMAGx
signals. For Paced Master mode, the data transfer is controlled
by ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAGx).
For Paced Master mode, the Memory Read-Bus Master, Mem-
ory Write-Bus Master, and Synchronous Read/Write-Bus
Master timing specifications for ADDR31–0, RDx, WRx,
MS3–0, PAGE, DATA63–0, and ACK also apply.
Table 26. DMA Handshake
Parameter
Timing Requirements
tSDRC
tWDR
tSDATDGL
tHDATIDG
tDATDRH
tDMARLL
tDMARH
DMARx Setup Before CLKIN1
DMARx Width Low (Nonsynchronous)2, 3
Data Setup After DMAGx Low4, 5
Data Hold After DMAGx High
Data Valid After DMARx High4, 6
DMARx Low Edge to Low Edge7
DMARx Width High2, 8
Min
3
0.5tCCLK+ 2.5
2
tCK
0.5tCCLK + 1
Max
tCK – 0.5tCCLK – 7
tCK+ 3
Unit
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
tDDGL
DMAGx Low Delay After CLKIN
0.25tCCLK + 1
0.25tCCLK + 9
ns
tWDGH
DMAGx High Width
0.5tCCLK – 1+ HI
ns
tWDGL
DMAGx Low Width
tCK – 0.5tCCLK – 1
ns
tHDGC
DMAGx High Delay After CLKIN
tCK – 0.25tCCLK + 1.5
tCK – 0.25tCCLK + 9
ns
tVDATDGH
Data Valid Before DMAGx High9
tCK – 0.25tCCLK – 8
tCK – 0.25tCCLK + 5
ns
tDATRDGH
Data Disable After DMAGx High10
0.25tCCLK – 3
0.25tCCLK+ 1.5
ns
tDGWRL
WRx Low Before DMAGx Low
–1.5
2
ns
tDGWRH
DMAGx Low Before WRx High
tCK – 0.5tCCLK – 2 + W
ns
tDGWRR
WRx High Before DMAGx High11
–1.5
2
ns
tDGRDL
RDx Low Before DMAGx Low
–1.5
2
ns
tDRDGH
RDx Low Before DMAGx High
tCK – 0.5tCCLK – 2+ W
ns
tDGRDR
RDx High Before DMAGx High11
–1.5
2
ns
tDGWR
DMAGx High to WRx, RDx, DMAGx Low
0.5tCCLK – 2+ HI
ns
tDADGH
Address/Select Valid to DMAGx High12
15.5
ns
tDDGHA
Address/Select Hold after DMAGx High
1
ns
W = (number of wait states specified in WAIT register) tCK.
HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1 Only required for recognition in the current cycle.
2 Maximum throughput using DMARx / DMAGx handshaking equals tWDR + tDMARH = (0.5tCCLK+ 1) + (0.5tCCLK+1)=10.0 ns (100 MHz). This throughput limit applies to
non-synchronous access mode only.
3 For ADSP-21160M, specification is tCCLK+4.5 ns, minimum.
4 tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven tDATDRH after DMARx is brought high.
5 For ADSP-21160M, specification is 0.75tCCLK–7 ns, maximum.
6 For ADSP-21160M, specification is tCLK+10 ns, maximum.
7 Use tDMARLL if DMARx transitions synchronous with CLKIN. Otherwise, use tWDR and tDMARH.
8 For ADSP-21160M, specification is tCCLK+4.5 ns, minimum.
9 tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = tCK – 0.25tCCLK – 8 + (n × tCK) where
n equals the number of extra cycles that the access is prolonged.
10See Example System Hold Time Calculation on page 49 for calculation of hold times given capacitive and dc loads.
11This parameter applies for synchronous access mode only.
12For ADSP-21160M, specification is 18 ns, minimum.
Rev. C | Page 39 of 60 | February 2013
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]