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ADSP-21266 View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADSP-21266
AD
Analog Devices AD
'ADSP-21266' PDF : 44 Pages View PDF
ADSP-21266
SPI Interface Protocol—Master
Table 30. SPI Interface Protocol—Master
Parameter
Min
Max
Timing Requirements
tSSPIDM
tHSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time)
5
SPICLK Last Sampling Edge to Data Input Not Valid
2
Switching Characteristics
tSPICLKM
tSPICHM
tSPICLM
tDDSPIDM
tHDSPIDM
tSDSCIM
tHDSM
tSPITDM
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
8 × tCCLK
4 × tCCLK – 2
4 × tCCLK – 2
3
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
10
FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge
Last SPICLK Edge to FLAG3–0 OUT High
Sequential Transfer Delay
4 × tCCLK – 2
4 × tCCLK – 1
4 × tCCLK – 1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLG3-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
MOSI
(OUTPUT)
CPHASE = 1
MISO
(INPUT)
tSD SCIM tSPICHM tSPIC LM
tS P IC LM
tSPICHM
tDDSPIDM
MSB
tSSPID M
MSB
VALID
tHSPIDM
MOSI
(OUTPUT)
CPHASE = 0
tSSPIDM
MISO
(INPUT)
MSB
tH S P ID M
MSB
VALID
tDDSPIDM
tS P IC LK M
tHDSM
tSPITDM
tHDSPIDM
tSSPIDM
tHDSPIDM
LSB
LSB
VALID
tHSPIDM
LSB
LSB
VALID
Figure 25. SPI Interface Protocol—Master
Rev. B | Page 34 of 44 | May 2005
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