ADSP-21362WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21362WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPI Interface—Slave
Table 39. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Timing Requirements
tSPICLKS
tSPICHS
tSPICLS
tSDSCO
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
tHDS
tSSPIDS
tHSPIDS
tSDPPW
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
Min
4 × tPCLK – 2
2 × tPCLK – 2
2 × tPCLK – 2
2 Ă— tPCLK
2 Ă— tPCLK
2 Ă— tPCLK
2
2
2 Ă— tPCLK
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
tDSOE
tDSOE1
SPIDS Assertion to Data Out Active
SPIDS Assertion to Data Out Active (SPI2)
0
5
ns
0
8
ns
tDSDHI
SPIDS Deassertion to Data High Impedance
0
tDSDHI1
SPIDS Deassertion to Data High Impedance (SPI2)
0
5
ns
8.6
ns
tDDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
9.5
ns
tHDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
2 Ă— tPCLK
ns
tDSOV
SPIDS Assertion to Data Out Valid (CPHASE = 0)
5 Ă— tPCLK
ns
1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-2136x SHARC Processor Hardware
Reference, “Serial Peripheral Interface Port” chapter.
Rev. A | Page 43 of 52 | December 2006
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