ADSP-21364WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21364WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPDIF Transmitter
Serial data input to the SPDIF transmitter can be formatted as
left-justified, I2S, or right-justified with word widths of 16, 18,
20, or 24 bits. The following sections provide timing for the
transmitter. This feature is not available on the
ADSP-21363 models.
SPDIF Transmitter—Serial Input Waveforms
Figure 29 shows the right-justified mode. LRCLK is HI for the
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
mode) from an LRCLK transition, so that when there are
64 SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
LRCLK
SCLK
SDATA
LS B
LEFT CHANNEL
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB
RIGHT CHANNEL
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB
Figure 29. Right -Justified Mode
Figure 30 shows the default I2S-justified mode. LRCLK is LO for
the left channel and HI for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
LRCLK
LEFT CHANNEL
RIGHT CHANNEL
SCLK
SDATA
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB
MSB
Figure 30. I2S-Justified Mode
Figure 31 shows the left-justified mode. LRCLK is HI for the left
channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.
LRCLK
SCLK
SDATA
MSB MSB-1 MSB-2
LEFT CHANNEL
RIGHT CHANNEL
LSB+2 LSB+1 LSB
MSB MSB-1 MSB-2
Figure 31. Left-Justified Mode
LSB+2 LSB+1 LSB
MSB MSB+1
Rev. A | Page 38 of 52 | December 2006
Share Link: 
