ADSP-21364WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21364WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table 35. Input signals (SCLK, FS, and SDATA) are routed to
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided below are valid at the DAI_P20–1 pins.
Table 35. SPDIF Transmitter Input Data Timing
Parameter
Min
Max
Unit
Timing Requirements
tSISFS1
FS Setup Before SCLK Rising Edge
3
ns
tSIHFS1
FS Hold After SCLK Rising Edge
3
ns
tSISD1
SDATA Setup Before SCLK Rising Edge
3
ns
tSIHD1
SDATA Hold After SCLK Rising Edge
3
ns
tSISCLKW
Clock Width
36
ns
tSISCLK
Clock Period
80
ns
tSITXCLKW
Transmit Clock Width
9
ns
tSITXCLK
Transmit Clock Period
20
ns
1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
DAI_P20-1
(TXCLK)
DAI_P20-1
(SCLK)
tSITXCLKW
tSISCLKW
tSITXCLK
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
tSISFS
tSISD
Figure 32. SPDIF Transmitter Input Timing
Oversampling Clock (TXCLK) Switching Characteristics
SPDIF Transmitter has an over sampling clock. This TXCLK
input is divided down to generate the biphase clock.
Table 36. Oversampling Clock (TXCLK) Switching Characteristics
Parameter
Min
TXCLK Frequency for TXCLK = 768 Ă— FS
TXCLK Frequency for TXCLK = 512 Ă— FS
TXCLK Frequency for TXCLK = 384 Ă— FS
TXCLK Frequency for TXCLK = 256 Ă— FS
Frame Rate
tSIHFS
tSIHD
Max
147.5
98.4
73.8
49.2
192.0
Unit
MHz
MHz
MHz
MHz
kHz
Rev. A | Page 39 of 52 | December 2006
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