ADSP-21364WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21364WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 – DAI_P20).
Table 20. Precision Clock Generator (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
tPCGIP
Input Clock Period
20
ns
tSTRIG
PCG Trigger Setup Before Falling
4.5
ns
Edge of PCG Input Clock
tHTRIG
PCG Trigger Hold After Falling
3
ns
Edge of PCG Input Clock
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active Edge
Delay After PCG Input Clock
2.5
10
ns
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger 2.5 + ((2.5 + D) Ă— tPCGIP)
10 + ((2.5 + D) Ă— tPCGIP)
ns
tDTRIGFS
PCG Frame Sync Delay After PCG Trigger
2.5 + ((2.5 + D – PH) × tPCGIP)
10 + ((2.5 + D – PH) × tPCGIP)
ns
tPCGOP
Output Clock Period
2 Ă— tPCGIP1
ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators”
chapter.
1 In normal mode, tPCGOP (min) = 2 Ă— tPCGIP.
tSTRIG
DAI_Pn
PCG_TRIGx_I
DAI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
PCG_CLKx_O
tHTRIG
tDPCGIO
tDTRIGCLK
tPCGIP
tDPCGIO
DAI_Pz
PCG_FSx_O
tDTRIGFS
Figure 16. Precision Clock Generator (Direct Pin Routing)
tPCGOP
Rev. A | Page 24 of 52 | December 2006
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