ADSP-21364WBBCZ-1A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21364WBBCZ-1A' PDF : 52 Pages View PDF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 25. 16-Bit Memory Write Cycle
Parameter
Min
Switching Characteristics
tALEW
tADAS1
tALERW
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
2 × tPCLK – 2.0
tPCLK – 2.5
2 × tPCLK – 3.8
tRWALE
tWRH2
tADAH1
tWW
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
WR Pulse Width
H + 0.5
F + H + tPCLK – 2.3
tPCLK – 2.3
D – F – 2.0
tDWS
AD15–0 Data Setup Before WR High
D – F + tPCLK – 4.0
tDWH
AD15–0 Data Hold After WR High
H
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK.
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × tPCLK.
tPCLK = (peripheral) clock period = 2 × tCCLK
1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
2 This parameter is only available when in EMPP = 0 mode.
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE
WR
RD
AD15-0
tALEW
tALERW
tWW
tRWALE
tWRH
tADAS
tADAH
VALID
ADDRESS
tDWH
VALID DATA
tDWS
VALID DATA
VALID
ADDRESS
NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP 0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.
Figure 21. Write Cycle for 16-Bit Memory Timing
Rev. A | Page 30 of 52 | December 2006
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