ADSP-21369 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21369' PDF : 60 Pages View PDF
Pulse-Width Modulation Generators
Table 35. PWM Timing
Parameter
Switching Characteristics
tPWMW
PWM Output Pulse Width
tPWMP
PWM Output Period
ADSP-21367/ADSP-21368/ADSP-21369
Min
tPCLK – 2
2 × tPCLK – 1.5
Max
(216 – 2) × tPCLK – 2
(216 – 1) × tPCLK – 1.5
Unit
ns
ns
PWM
OUTPUTS
tPWMW
tP W MP
Figure 26. PWM Timing
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in Table 36 are valid at the DAI_P20–1 pins.
Table 36. SRC, Serial Input Port
Parameter
Min
Max
Unit
Timing Requirements
t1
SRCSFS
FS Setup Before SCLK Rising Edge
4
ns
t1
SRCHFS
FS Hold After SCLK Rising Edge
5.5
ns
t1
SRCSD
SDATA Setup Before SCLK Rising Edge
4
ns
t1
SRCHD
SDATA Hold After SCLK Rising Edge
5.5
ns
tSRCCLKW
Clock Width
9
ns
tSRCCLK
Clock Period
20
ns
1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
tSR CCLKW
SAMPLE EDGE
tSRCCLK
tSRCSFS
tSRCHFS
tSRCSD
tSRCHD
Figure 27. SRC Serial Input Port Timing
Rev. C | Page 37 of 56 | January 2008
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