ADSP-21369 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21369' PDF : 60 Pages View PDF
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 40. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter
Switching Characteristics
tDFSI
tHOFSI
tDDTI
tHDTI
t1
SCLKIW
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
1 SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
ADSP-21367/ADSP-21368/ADSP-21369
Min
Max
Unit
5
ns
–2
ns
5
ns
–2
ns
40
ns
DRIVE EDGE
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
tHOFSI
tHDTI
tDFSI
tSCLKIW
tDDTI
SAMPLE EDGE
Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. C | Page 41 of 56 | January 2008
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