ADSP-21369 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21369' PDF : 60 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
SPI Interface—Master
The processors contain two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DPI. The
timing provided in Table 41 and Table 42 on Page 43 applies
to both.
Table 41. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time)
tHSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid
Switching Characteristics
tSPICLKM
tSPICHM
tSPICLM
tDDSPIDM
tHDSPIDM
tSDSCIM
tHDSM
tSPITDM
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
Last SPICLK Edge to FLAG3–0IN High
Sequential Transfer Delay
Min
8.2
2
8 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 1
Max
2.5
FLAG3-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
MOSI
(OUTPUT)
CPHASE = 1
MISO
(INPUT)
tSDSCIM tSPICHM tSPICLM
tSPICLM
tSPICHM
tD DS P I DM
MSB
tSSPIDM
tHSPIDM
MSB
VALID
MOSI
(OUTPUT)
CPHASE = 0
tSSPIDM
MISO
(INPUT)
MSB
tHSPIDM
MSB
VALID
tDDSPIDM
tSPICLKM
tHDSM
tSPITDM
t HDSPIDM
tSSPIDM
tHDSPIDM
LSB
LSB
VALID
tHSPIDM
LSB
LSB
VALID
Figure 34. SPI Master Timing
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. C | Page 42 of 56 | January 2008
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