ADSP-21369 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21369' PDF : 56 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
SPI Interface—Slave
Table 42. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Min
Max
Unit
Timing Requirements
tSPICLKS
Serial Clock Cycle
4 × tPCLK – 2
ns
tSPICHS
Serial Clock High Period
2 × tPCLK – 2
ns
tSPICLS
Serial Clock Low Period
2 × tPCLK – 2
ns
tSDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
2 × tPCLK
ns
2 × tPCLK
ns
tHDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
2 × tPCLK
ns
tSSPIDS
Data Input Valid to SPICLK Edge (Data Input Setup Time)
2
ns
tHSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
2
ns
tSDPPW
SPIDS Deassertion Pulse Width (CPHASE = 0)
2 × tPCLK
ns
Switching Characteristics
tDSOE
t1
DSOE
tDSDHI
t1
DSDHI
tDDSPIDS
tHDSPIDS
tDSOV
SPIDS Assertion to Data Out Active
SPIDS Assertion to Data Out Active (SPI2)
SPIDS Deassertion to Data High Impedance
SPIDS Deassertion to Data High Impedance (SPI2)
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
0
0
0
0
2 × tPCLK
6.8
ns
8
ns
6.8
ns
8.6
ns
9.5
ns
ns
5 × tPCLK
ns
1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-21368 SHARC Processor Hardware
Reference, “Serial Peripheral Interface Port” chapter.
Rev. C | Page 43 of 56 | January 2008
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