ADSP-21369 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21369' PDF : 56 Pages View PDF
ADSP-21367/ADSP-21368/ADSP-21369
OUTPUT DRIVE CURRENTS
Figure 37 shows typical I-V characteristics for the output driv-
ers and Figure 38 shows typical I-V characteristics for the
SDCLK output drivers. The curves represent the current drive
capability of the output drivers as a function of output voltage.
40
30
VOH
3.3V, 25°C
20
10
3.11V, 125°C
0
3.47V, -45°C
3.11V, 105°C
-10
3.11V, 125°C
-20
-30
-40
0
VOL
0.5
3.47V, -45°C
1.0
1.5 2.0
2.5
SWEEP (VDDEXT) VOLTAGE (V)
3.11V, 105°C
3.3V, 25°C
3.0
3.5
Figure 37. Typical Drive at Junction Temperature
75
60
VOH
45
30
3 .1 3 V, 12 5 °C
15
3 .47 V, -45 °C
3.3 V, 25 °C
3.1 3V, 1 05 °C
0
-15
-30
-45
3.1 3V, 1 25 °C
3 .1 3 V, 10 5° C
-60
-75
-90
3.3 V, 2 5°C
3 .47 V, -4 5°C
VOL
-1 0 5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SW EEP (VDDEXT) VOLTAGE (V)
Figure 38. SDCLK1–0 Drive at Junction Temperature
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 15 on Page 21 through Table 43 on Page 45. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 39.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 39. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
INPUT
OR
1.5V
OUTPUT
1.5V
Figure 39. Voltage Reference Levels for AC Measurements
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 40). Figure 45 and
Figure 46 show graphically how output delays and holds vary
with load capacitance. The graphs of Figure 41 through
Figure 46 may not be linear outside the ranges shown for Typi-
cal Output Delay vs. Load Capacitance and Typical Output Rise
Time (20% to 80%, V = Min) vs. Load Capacitance.
1.5V
4pF
70:
50:
2pF
400:
TESTER PIN ELECTRONICS
45:
0.5pF
T1
DUT
OUTPUT
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 40. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Rev. C | Page 46 of 56 | January 2008
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