ADSP-2141L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2141L' PDF : 39 Pages View PDF
• IRQ2 now can include interrupt sources from the crypto
subsystem, depending on interrupt mask registers.
• A new read register has been added to indicate the state of
interrupt enable and interrupt masks.
• The kernel mode control subsystem has been added to super-
vise the protected mode of operation of the DSP core.
• Internal RAM protection logic has been added to allow the
kernel to seize increments of 1K word of internal PRAM and
DRAM.
• Bus mode configuration (218x vs. PCI) pins have been added.
• 32K words of kernel program ROM have been added to the
DSP memory space. (See the Memory Map section.)
Kernel Mode Control
The kernel mode control subsystem provides the following
functions which serve to enforce the security integrity of the
ADSP-2141L:
• Provide a means to securely enter the kernel mode.
• Provide a means to properly exit the kernel mode.
• Prevent user mode access to protected memory and register
locations.
• Manage interrupts during kernel mode executions.
• Manage the reset function to ensure that sensitive variables
in DSP registers are erased.
Most of the kernel mode control functions are implemented in
the hardware of the ADSP-2141L and are not directly visible to
nonkernel applications (user mode). Any attempt by a user
mode application program running on the DSP to access a
kernel space addresses (PRAM 0x2001 – 0x3FFF, PMOVLAY
000C – 000F; or DRAM 0x0000 – 0x17FF, DMOVLAY 000F)
results in an immediate chip reset and all sensitive registers and
memory locations are erased. Kernel mode may only be entered
via a call, jump or increment to address 0x2000 with PMOVLAY
REGISTER
ADDRESS
7
WR
ADSP-2141L
set to 0x000F. Once in kernel mode, any branch to nonkernel
space program memory causes the DSP to return to user mode.
(Note: For security reasons when in kernel mode, the DSP does
not respond to Emulator bus requests.)
The kernel mode can be interrupted during execution; however,
during certain periods where sensitive data is being moved, all
interrupts are disabled. Within the interrupt service routine,
another call to the kernel (CGX call) may be made if desired,
although there are limitations on which CGX commands may
preempt another. (For information, see the ADSP-2141L CGX
Interface Programmer’s Guide http://www.ire-ma.com/proddoc.htm.)
Only one level of kernel mode nesting is permitted. An interrupt
to a user mode vector location while in nested kernel mode will
also trigger the violation reset logic.
Once the interrupt service routine is finished, the return-from-
interrupt must return control back to the kernel at the address/
overlay that was originally interrupted, otherwise the protection
logic will issue a chip reset.
Hash and Encrypt Block Overview
The encrypt block is tightly coupled to the hash block in the
ADSP-2141L and therefore the two are discussed together.
Refer to Figure 4, Hash/Encrypt Functional Block Diagram, for
the following description.
The algorithms implemented in the combined hash and encryp-
tion block are: DES, Triple DES, MD-5 and SHA-1. Data can
be transferred to and from the module once to perform both
hashing and encryption on the same data stream. The DES
encrypt/decrypt operations are highly paralleled and pipelined,
and execute full 16-round DES in only four clock cycles. The
internal data flow and buffering allows parallel execution of
hashing and encryption where possible, and allows processing of
data concurrently with I/O of previous and subsequent blocks.
RD
DSP
OR
PCI
16-/32-BIT
INPUT
BUS
PAD
INSERTION
512-BIT
FIFO
PAD
CONSUME
AND VERIFY
ENCRYPT/
DECRYPT
BLOCK
WRITE
CONTEXT
512-BIT
FIFO
CONTEXT
STORAGE (0/1)
HASH
BLOCK
READ
CONTEXT
HASH
DIGEST
DSP
OR
PCI
16-/32-BIT
OUTPUT
BUS
REV. 0
MUTABLE BIT
PAD
PROCESSING INSERTION
(ENCRYPT-THEN-HASH)
(DECRYPT-THEN-HASH)
Figure 4. Hash/Encrypt Functional Block Diagram
–5–
Share Link: 
