ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
ADSP-21467/ADSP-21469
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 – DAI_P20).
Table 27. Precision Clock Generator (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
tPCGIW
Input Clock Period
tPCLK × 4
ns
tSTRIG
PCG Trigger Setup Before Falling Edge of PCG Input 4.5
ns
Clock
tHTRIG
PCG Trigger Hold After Falling Edge of PCG Input 3
ns
Clock
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active Edge Delay 2.5
10
After PCG Input Clock
ns
tDTRIGCLK PCG Output Clock Delay After PCG Trigger
2.5 + (2.5 × tPCGIP)
10 + (2.5 × tPCGIP)
ns
tDTRIGFS
tPCGOW1
PCG Frame Sync Delay After PCG Trigger
Output Clock Period
2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) ns
2 × tPCGIP – 1
ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators”
chapter.
1 Normal mode of operation.
tSTRIG
DAI_Pn
DPI_Pn
PCG_TRIGx_I
tHTRIG
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
DPI_Py
PCG_CLKx_O
DAI_Pz
DPI_Pz
PCG_FSx_O
tDPCGIO
tPCGIP
tDTRIGCLK
tDPCGIO
tPCGOW
tDTRIGFS
Figure 16. Precision Clock Generator (Direct Pin Routing)
Rev. B | Page 31 of 76 | March 2013
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