ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
ADSP-21467/ADSP-21469
DDR2 SDRAM Read Cycle Timing
Table 29. DDR2 SDRAM Read Cycle Timing, VDD_DDR2 Nominal 1.8 V
200 MHz1
225 MHz1
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tAC
Access Window of DDR2_DATA to
DDR2_CLKx/DDR2_CLKx
–1.0
1.5
–1.0
1.5
ns
tDQSCK
Access Window of DDR2_DQSx/DDR2_DQSx to –1.0
1.5
–1.0
1.5
ns
DDR2_CLKx/DDR2_CLKx
tDQSQ
DQS-DATA skew for DDR2_DQSx and Associated
DDR2_DATA signals
0.450
0.450
ns
tQH
DDR2_DATA Hold Time From
1.9
DDR2_DQSx/DDR2_DQSx
1.71
ns
tRPRE
Read Preamble
tRPST
Read Postamble
Switching Characteristics
0.6
0.6
tCK
0.25
0.25
tCK
tCK
DDR2_CLKx/DDR2_CLKx Period
4.8
4.22
ns
tCH
DDR2_CLKx High Pulse Width
2.35
2.75
2.05
2.45
ns
tCL
DDR2_CLKx Low Pulse Width
2.35
2.75
2.05
2.45
ns
tAS
DDR2_ADDR and Control Setup Time Relative to 1.85
1.65
ns
DDR2_CLKx Rising
tAH
DDR2_ADDR and Control Hold Time Relative to 1.0
0.9
ns
DDR2_CLKx Rising
1 In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed (see Engineer-to-Engineer Note EE-349).
DDR2_CLKx
DDR2_CLKx
DDR2_ADDR
DDR2_CTL
DDR2_DQSn
DDR2_DQSn
DDR2_DATA
tCK
tCH
tCL
tAS
tAH
tAC
tRPRE
tDQSCK
tDQSQ
tQH
tDQSQ
tRPST
tQH
Figure 18. DDR2 SDRAM Controller Input AC Timing
Rev. B | Page 33 of 76 | March 2013
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