ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
ADSP-21467/ADSP-21469
Sample Rate Converter—Serial Output Port
For the serial output port, the frame sync is an input and it
should meet setup and hold times with regard to the serial clock
on the output port. The serial data output has a hold time and
delay specification with regard to serial clock. Note that the
serial clock rising edge is the sampling edge, and the falling edge
is the drive edge.
Table 45. ASRC, Serial Output Port
Parameter
Min
Max
Unit
Timing Requirements
tSRCSFS1
Frame Sync Setup Before Serial Clock Rising Edge
4
ns
tSRCHFS1
Frame Sync Hold After Serial Clock Rising Edge
5.5
ns
tSRCCLKW
tSRCCLK
Clock Width
Clock Period
(tPCLK × 4) ÷ 2 – 1
ns
tPCLK × 4
ns
Switching Characteristics
tSRCTDD1
Transmit Data Delay After Serial Clock Falling Edge
tSRCTDH1
Transmit Data Hold After Serial Clock Falling Edge
1
9.9
ns
ns
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The PCG’s
input can be either CLKIN or any of the DAI pins.
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
SAMPLE EDGE
tSRCCLKW
tSRCCLK
tSRCSFS
tSRCHFS
tSRCTDD
tSRCTDH
Figure 33. ASRC Serial Output Port Timing
Rev. B | Page 50 of 76 | March 2013
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