ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 76 Pages View PDF
ADSP-21467/ADSP-21469
Table 10. Pin Descriptions (Continued)
Name
Type
State During/ After
Reset
Description
BR2-1
I/P (ipu)
BR1 = driven low by Bus request. Used by the processor to arbitrate for bus mastership. A processor only
the processor with drives its own BRx line (corresponding to the value of its ID1–0 inputs) and monitors
(ID1=0, ID0=1)
all others. The processor’s own BRx line must not be tied high or low because it is an
BR2 = driven high by output.
the processor with
(ID1=1, ID0=0)
BR2–1 = High-Z if ID
pins are at zero
ID1-0
I
Chip ID. Determines which bus request (BR2-1) is used by the processor. ID = 00
corresponds to BR1 and ID = 10 corresponds to BR2. Use ID = 00 or 01 in single-
processor systems. These lines are a system configuration selection that should be
hardwired or only changed at reset. ID = 11 is reserved.
TDI
I (ipu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO
O /T
High-Z
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
I (ipu)
Test Mode Select (JTAG). Used to control the test state machine.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK signal must be
asserted (pulsed low) after power-up or held low for proper operation of the device.
TRST
I (ipu)
Test Reset (JTAG). Resets the test state machine. The TRST signal must be asserted
(pulsed low) after power-up or held low for proper operation of the processor.
EMU
O/D (ipu)
High-Z
Emulation Status. Must be connected to the ADSP-21467/ADSP-21469 Analog
Devices DSP Tools product line of JTAG emulators target board connector only.
CLK_CFG1–0
I
Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that
the operating frequency can be changed by programming the PLL multiplier and
divider in the PMCTL register at any time after the core comes out of reset. The allowed
values are:
00 = 6:1
01 = 32:1
10 = 16:1
11 = reserved
CLKIN
I
Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures
the processor to use either its internal clock generator or an external clock source.
Connecting the necessary components to CLKIN and XTAL enables the internal clock
generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the processor to use the external clock source such as an external clock
oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
XTAL
O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–
63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at
typical conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.
Rev. B | Page 17 of 76 | March 2013
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