ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 76 Pages View PDF
ADSP-21467/ADSP-21469
Serial Ports
In slave transmitter mode and master receiver mode the maxi-
mum serial port frequency is fPCLK/8. To determine whether
communication is possible between two devices at clock speed
n, the following specifications must be confirmed: 1) frame sync
delay and frame sync setup and hold, 2) data delay and data
setup and hold, and 3) serial clock (SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins. In Figure 26 either the rising edge
or the falling edge of SCLK (external or internal) can be used as
the active sampling edge.
Table 37. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tHFSE1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tSDRE1
Receive Data Setup Before Receive SCLK
tHDRE1
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Switching Characteristics
tDFSE2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
tHOFSE2 Frame Sync Hold After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
tDDTE2
Transmit Data Delay After Transmit SCLK
tHDTE2
Transmit Data Hold After Transmit SCLK
1 Referenced to sample edge.
2 Referenced to drive edge.
Min
2.5
2.5
1.9
2.5
(tPCLK × 4) ÷ 2 – 1.2
tPCLK × 4
2
2
Max
10.25
8.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 38. Serial Ports—Internal Clock
Parameter
Min
Timing Requirements
tSFSI1
Frame Sync Setup Before SCLK
7
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tHFSI1
Frame Sync Hold After SCLK
2.5
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tSDRI1
Receive Data Setup Before SCLK
7
tHDRI1
Receive Data Hold After SCLK
2.5
Switching Characteristics
tDFSI2
tHOFSI2
tDFSIR2
tHOFSIR2
tDDTI2
tHDTI2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
–1.25
tSCLKIW Transmit or Receive SCLK Width
2 × tPCLK – 1.2
1 Referenced to the sample edge.
2 Referenced to drive edge.
Max
Unit
ns
ns
ns
ns
4
ns
ns
9.75
ns
ns
3.25
ns
ns
2 × tPCLK + 1.5 ns
Rev. B | Page 42 of 76 | March 2013
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