ADSP-21469KBCZ-3 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBCZ-3' PDF : 72 Pages View PDF
ADSP-21467/ADSP-21469
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 42. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 42. Input Data Port (IDP)
Parameter
Min
Max
Unit
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge
3.8
ns
tSIHFS1
Frame Sync Hold After Serial Clock Rising Edge
2.5
ns
tSISD1
Data Setup Before Serial Clock Rising Edge
2.5
ns
tSIHD1
Data Hold After Serial Clock Rising Edge
2.5
ns
tIDPCLKW
Clock Width
(tPCLK × 4) ÷ 2 – 1
ns
tIDPCLK
Clock Period
tPCLK × 4
ns
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The PCG’s input
can be either CLKIN or any of the DAI pins.
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
SAMPLE EDGE
tIDPCLKW
tIDPCLK
tSISFS
tSIHFS
tSISD
tSIHD
Figure 30. IDP Master Timing
Rev. B | Page 47 of 76 | March 2013
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