ADSP-21469KBCZ-3 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBCZ-3' PDF : 72 Pages View PDF
ADSP-21467/ADSP-21469
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 43. PDAP is the parallel mode operation of channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-214xx SHARC Processor Hardware
Reference.
Table 43. Parallel Data Acquisition Port (PDAP)
Parameter
Min
Max
Unit
Timing Requirements
tSPHOLD1
PDAP_HOLD Setup Before PDAP_CLK Sample Edge
2.5
ns
tHPHOLD1
PDAP_HOLD Hold After PDAP_CLK Sample Edge
2.5
ns
tPDSD1
PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge
3.85
ns
tPDHD1
PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge
2.5
ns
tPDCLKW
Clock Width
(tPCLK × 4) ÷ 2 – 3
ns
tPDCLK
Clock Period
tPCLK × 4
ns
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
2 × tPCLK + 3
ns
tPDSTRB
PDAP Strobe Pulse Width
2 × tPCLK – 1
ns
1 The 20 bits of external PDAP data can be provided through the AMI_ADDR23–4 or DAI pins. Source pins for serial clock and frame sync are 1) AMI_ADDR3–2 pins, 2)
DAI pins.
DAI_P20–1
(PDAP_CLK)
DAI_P20–1
(PDAP_HOLD)
DAI_P20–1/
ADDR23–4
(PDAP_DATA)
DAI_P20–1
(PDAP_STROBE)
SAMPLE EDGE
tPDCLKW
tPDCLK
tSPHOLD
tHPHOLD
tPDSD
tPDHD
tPDHLDD
tPDSTRB
Figure 31. PDAP Timing
Rev. B | Page 48 of 76 | March 2013
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