ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Shift Register
Table 54. Shift Register
Parameter
Min
Max
Unit
Timing Requirements
tSSDI
SR_SDI Setup Before SR_SCLK Rising Edge
tHSDI
SR_SDI Hold After SR_SCLK Rising Edge
tSSDIDAI1
DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge
tHSDIDAI1
DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge
tSSCK2LCK2
SR_SCLK to SR_LAT Setup
tSSCK2LCKDAI1, 2
DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup
tCLRREM2SCK
Removal Time SR_CLR to SR_SCLK
tCLRREM2LCK
Removal Time SR_CLR to SR_LAT
tCLRW
SR_CLR Pulse Width
tSCKW
SR_SCLK Clock Pulse Width
tLCKW
SR_LAT Clock Pulse Width
fMAX
Maximum Clock Frequency SR_SCLK or SR_LAT
Switching Characteristics
7
2
7
2
2
2
3 × tPCLK – 5
2 × tPCLK – 5
4 × tPCLK – 5
2 × tPCLK – 2
2 × tPCLK – 5
fPCLK 4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
tDSDO13
SR_SDO Hold After SR_SCLK Rising Edge
3
ns
tDSDO23
SR_SDO Max. Delay After SR_SCLK Rising Edge
13
ns
tDSDODAI11, 3
SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge
3
ns
tDSDODAI21, 3
SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge
13
ns
tDSDOSP13, 4
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge
–2
ns
tDSDOSP23, 4
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge
5
ns
tDSDOPCG13, 5, 6
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge
–2
ns
tDSDOPCG23, 5, 6
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge
5
ns
tDSDOCLR13
SR_CLR to SR_SDO Min. Delay
4
ns
tDSDOCLR23
SR_CLR to SR_SDO Max. Delay
13
ns
tDLDO13
SR_LDO Hold After SR_LAT Rising Edge
3
ns
tDLDO23
SR_LDO Max. Delay After SR_LAT Rising Edge
13
ns
tDLDODAI13
SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge
3
ns
tDLDODAI23
SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge
13
ns
tDLDOSP13, 4
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge
–2
ns
tDLDOSP23, 4
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge
5
ns
tDLDOPCG13, 5, 6
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge
–2
ns
tDLDOPCG23, 5, 6
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge
5
ns
tDLDOCLR13
SR_CLR to SR_LDO Min. Delay
4
ns
tDLDOCLR23
SR_CLR to SR_LDO Max. Delay
14
ns
1 Any of the DAI_P08–01 pins can be routed to the shift register clock, latch clock and serial data input via the SRU.
2 Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of
latch register data.
3 For setup/hold timing requirements of off-chip shift register interfacing devices.
4 SPORTx serial clock out, frame sync out, and serial data outputs are routed to shift register block internally and are also routed onto DAI_P20–01.
5 PCG serial clock output is routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally.
6 PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally.
Rev. C | Page 61 of 76 | July 2013
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