ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
For information on the UART port receive and transmit opera-
tions, see the ADSP-214xx SHARC Hardware Reference Manual.
2-Wire Interface (TWI)—Receive and Transmit Timing
For information on the TWI receive and transmit operations,
see the ADSP-214xx SHARC Hardware Reference Manual.
JTAG Test Access Port and Emulation
Table 55. JTAG Test Access Port and Emulation
88-Lead LFCSP Package
All Other Packages
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
20
ns
tSTAP
TDI, TMS Setup Before TCK High
5
5
ns
tHTAP
TDI, TMS Hold After TCK High
6
6
ns
tSSYS1
System Inputs Setup Before TCK High
7
7
ns
tHSYS1
System Inputs Hold After TCK High
18
18
ns
tTRSTW
TRST Pulse Width
4 × tCK
4 × tCK
ns
Switching Characteristics
tDTDO
tDSYS2
TDO Delay from TCK Low
System Outputs Delay After TCK Low
11.5
tCK ÷ 2 + 7
10.5
ns
tCK ÷ 2 + 7
ns
1 System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG1–0, DAI_Px, DPI_Px, FLAG3–0, MLBCLK, MLBDAT, MLBSIG, SR_SCLK, SR_CLR, SR_SDI, and
SR_LAT.
2 System Outputs = DAI_Px, DPI_Px, ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK, MLBDAT, MLBSIG, MLBDO,
MLBSO, SR_SDO, SR_LDO, and EMU.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tDTDO
tSTAP
tSSYS
tDSYS
tHTAP
tHSYS
Figure 46. IEEE 1149.1 JTAG Test Access Port
Rev. C | Page 64 of 76 | July 2013
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