ADSP-2184L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2184L' PDF : 31 Pages View PDF
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Clock Signals and Reset
Table 14. Clock Signals and Reset
ADSP-2184L, ADSP-2186L
ADSP-2185L, ADSP-2187L
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tCKI
CLKIN Period
tCKIL
CLKIN Width Low
tCKIH
CLKIN Width High
Switching Characteristics:
50
150
38
20
15
20
15
100
ns
ns
ns
tCKL
CLKOUT Width Low
0.5tCK – 7
0.5tCK – 7
ns
tCKH
CLKOUT Width High
0.5tCK – 7
0.5tCK – 7
ns
tCKOH
CLKIN High to CLKOUT High
0
20
0
20
ns
Control Signals Timing Requirements:
tRSP
RESET Width Low1
5tCK
5tCK
ns
tMS
Mode Setup Before RESET High
2
2
ns
tMH
Mode Hold After RESET High
5
5
ns
1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator
start-up time).
CLKIN
CLKOUT
tCKI
tCKIH
tCKIL
tCKOH
tCKH
tCKL
MODE A D
RESET
tMS
tMH
tRSP
Figure 16. Clock Signals and Reset
Rev. C | Page 23 of 48 | January 2008
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