ADSP-2184L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2184L' PDF : 31 Pages View PDF
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Memory Read
Table 17. Memory Read
Parameter
Timing Requirements:
tRDD
RD Low to Data Valid1
tAA
A13–0, xMS to Data Valid2
tRDH
Data Hold from RD High3
Switching Characteristics:
tRP
RD Pulse Width
tCRD
CLKOUT High to RD Low
tASR
A13–0, xMS Setup Before RD Low
tRDA
A13–0, xMS Hold After RD Deasserted
tRWR
RD High to RD or WR Low
1 w = wait states × tCK.
2 xMS = PMS, DMS, CMS, IOMS, BMS.
3 For the ADSP-2187L, this specification is 0 ns min.
Min
1
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK – 6
0.25tCK – 3
0.5tCK – 5
Max
0.5tCK – 9 + w
0.75tCK – 12.5 + w
0.25tCK + 7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
ADDRESS LINES1
DMS, PMS,
BMS, IOMS,
CMS
RD
DATA LINES2
tASR
tCRD
tAA
WR
1ADDRESS LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs)
I/O SPACE: A10–0
EXTERNAL PM AND DM: A13–0
tRP
tR DD
tRDA
tRWR
tRDH
2DATA LINES FOR ACCESSES ARE:
BDMA: D15–8
I/O SPACE: D23–8
EXTERNAL DM: D23–8
EXTERNAL PM: D23–0
Figure 19. Memory Read
Rev. C | Page 26 of 48 | January 2008
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