Timer PWM_OUT Cycle Timing
Table 8 and Figure 9 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and has
an absolute maximum input frequency of 40 MHz.
Table 8. Timer PWM_OUT Cycle Timing
Parameter
Switching Characteristic
tHTO
Timer Pulse Width Output1
1 The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232 –1) cycles.
Min
12.5
HCLK
PWM_OUT
tHTO
Figure 9. Timer PWM_OUT Cycle Timing
ADSP-21990
Max
(232 –1) cycles
Unit
ns
Rev. A | Page 27 of 50 | August 2007