ADSP-21990 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21990' PDF : 50 Pages View PDF
ADSP-21990
External Port Read Cycle Timing
Table 10 and Figure 11 describe external port read operations.
For additional information on the ACK signal, see the discus-
sion on Page 28.
Table 10. External Port Read Cycle Timing
Parameter1, 2
Timing Requirements
tAKW
tRDA
tADA
tSDA
tSD
tHRD
tDRSAK
ACK Strobe Pulse Width
RD Asserted to Data Access Setup
Address Valid to Data Access Setup
Chip Select Asserted to Data Access Setup
Data Valid to RD Deasserted Setup
RD Deasserted to Data Invalid Hold
ACK Delay from XMS Low
Switching Characteristics
tCSRS
Chip Select Asserted to RD Asserted Delay
tARS
Address Valid to RD Setup and Delay
tRSCS
RD Deasserted to Chip Select Deasserted Setup
tRW
RD Strobe Pulse Width
tRSA
RD Deasserted to Address Invalid Setup
tRWR
RD Deasserted to WR, RD Asserted
1 tEMICLK is the external memory interface clock period. tHCLK is the peripheral clock period.
2 These are timing parameters that are based on worst-case operating conditions.
3 W = (number of wait states specified in wait register) ؋ tEMICLK.
Min
tHCLK
5
0
0.5tEMICLK – 3
0.5tEMICLK – 3
0.5tEMICLK – 2
tEMICLK – 2 + W3
0.5tHCLK – 2
tHCLK
Max
tEMICLK – 5 + W3
tEMICLK + W3
tEMICLK + W3
0.5tEMICLK – 1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 30 of 50 | August 2007
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