ADSP-BF516KSWZ-4 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF516KSWZ-4' PDF : 68 Pages View PDF
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
External DMA Request Timing
Table 29 and Figure 13 describe the External DMA Request
operations.
Table 29. External DMA Request Timing1
VDDMEM/VDDEXT
1.8 V Nominal
VDDMEM/VDDEXT
2.5 V/3.3 V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing PRequirements
tDR
DMARx Asserted to CLKOUT High Setup
9
7.2
ns
tDH
CLKOUT High to DMARx Deasserted Hold Time
0
0
ns
tDMARACT
DMARx Active Pulse Width
tSCLK + 1
tSCLK + 1
ns
tDMARINACT DMARx Inactive Pulse Width
1.75 × tSCLK
1.75 × tSCLK
ns
1 Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and
VDDMEM are NOT equal may require level shifting logic for correct operation.
CLKOUT
DMAR0/1
(ACTIVE LOW)
DMAR0/1
(ACTIVE HIGH)
tDS
tDH
tDMARACT
tDMARINACT
Figure 13. External DMA Request Timing
Rev. B | Page 32 of 68 | January 2011
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