ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
RSCLKx
tHOFSI
RFSx
(OUTPUT)
RFSx
(INPUT)
DRx
tSCLKIW
tDFSI
tSFSI
tSDRI
tHFSI
tHDRI
RSCLKx
tHOFSE
RFSx
(OUTPUT)
RFSx
(INPUT)
DRx
tSCLKEW
tDFSE
tSFSE
tSDRE
tSCLKE
tHFSE
tHDRE
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
TSCLKx
SAMPLE EDGE
tHOFSI
TFSx
(OUTPUT)
tD FSI
TFSx
(INPUT)
DTx
tHDTI
tDDTI
tSFSI
tHFSI
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
tSCLKE
t SCLKEW
TSCLKx
tHOFSE
TFSx
(OUTPUT)
tDFSE
TFSx
(INPUT)
DTx
tHDTE
tDDTE
tSFSE
tHFSE
Figure 21. Serial Ports
TSCLKx
(INPUT)
TFSx
(INPUT)
tSUDTE
RSCLKx
(INPUT)
RFSx
(INPUT)
tSUDRE
FIRST
Figure 22. Serial Port Start Up with External Clock and Frame Sync
Rev. B | Page 38 of 68 | January 2011