ADSP-BF516KSWZ-4 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF516KSWZ-4' PDF : 68 Pages View PDF
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 44. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Parameter1
VDDEXT
1.8V Nominal
Min
Max
Switching Characteristics
tETF
tETXCLKW
tETXCLKOV
tETXCLKOH
ETxCLK Frequency (fSCLK = SCLK Frequency)
None
ETxCLK Width (tETxCLK = ETxCLK Period)
tETxCLK × 40%
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
25 + 1%
tETxCLK × 60%
20
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold) 0
1 MII outputs synchronous to ETxCLK are ETxD3–0.
VDDEXT
2.5 V/3.3V Nominal
Min
Max
None
25 + 1%
tETxCLK × 35% tETxCLK × 65%
20
0
Unit
MHz
ns
ns
ns
MIITxCLK
ETxD3–0
ETxEN
tETXCLKW
tETXCLKOH
tETXCLK
tETXCLKOV
Figure 32. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Table 45. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter1
VDDEXT
1.8V Nominal
Min
Max
Timing Requirements
tEREFCLKF
tEREFCLKW
tEREFCLKIS
REF_CLK Frequency (fSCLK = SCLK Frequency)
EREF_CLK Width (tEREFCLK = EREFCLK Period)
Rx Input Valid to RMII REF_CLK Rising Edge (Data In
Setup)
None
50 + 1%
tEREFCLK × 40% tEREFCLK × 60%
4
tEREFCLKIH
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In 2
Hold)
1 RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
VDDEXT
2.5 V/3.3V Nominal
Min
Max
None
50 + 1%
tEREFCLK × 35% tEREFCLK × 65%
4
2
Unit
MHz
ns
ns
ns
RMII_REF_CLK
tREFCLKW
tREFCLK
ERxD1–0
ERxDV
ERxER
tREFCLKIS tREFCLKIH
Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Rev. B | Page 46 of 68 | January 2011
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