ADSP-BF516KSWZ-4 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF516KSWZ-4' PDF : 68 Pages View PDF
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 47. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter
Min
Max
Unit
Timing Requirements
tECOLH
tECOLL
tECRSH
tECRSL
COL Pulse Width High1
COL Pulse Width Low1
CRS Pulse Width High2
CRS Pulse Width Low2
tETxCLK × 1.5
ns
tERxCLK × 1.5
ns
tETxCLK × 1.5
ns
tERxCLK × 1.5
ns
tETxCLK × 1.5
ns
tETxCLK × 1.5
ns
1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2 The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
MIICRS, COL
tECRSH
tECOLH
tECRSL
tECOLL
Figure 35. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
Table 48. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter1
Min
Max
Unit
Timing Requirements
tMDIOS
MDIO Input Valid to MDC Rising Edge (Setup)
tMDCIH
MDC Rising Edge to MDIO Input Invalid (Hold)
Switching Characteristics
11.5
ns
0
ns
tMDCOV
tMDCOH
MDC Falling Edge to MDIO Output Valid
MDC Falling Edge to MDIO Output Invalid (Hold)
25
ns
–1.25
ns
1 MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
MDC (OUTPUT)
MDIO (OUTPUT)
tMDCOH
tMDCOV
MDIO (INPUT)
tMDIOS
tMDCIH
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Station Management
Rev. B | Page 48 of 68 | January 2011
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