ADSP-BF522BBCZ-3A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF522BBCZ-3A' PDF : 88 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
NAND Flash Controller Interface Timing
Table 36 and Figure 13 on Page 44 through Figure 17 on
Page 46 describe NAND Flash Controller Interface operations.
Table 36. NAND Flash Controller Interface Timing
Parameter
Write Cycle
Switching Characteristics
tCWL
tCH
tCLEWL
tCLH
tALEWL
tALH
tWP1
tWHWL
tWC1
tDWS1
tDWH
Read Cycle
ND_CE Setup Time to AWE Low
ND_CE Hold Time From AWE High
ND_CLE Setup Time to AWE Low
ND_CLE Hold Time From AWE high
ND_ALE Setup Time to AWE Low
ND_ALE Hold Time From AWE High
AWE Low to AWE high
AWE High to AWE Low
AWE Low to AWE Low
Data Setup Time for a Write Access
Data Hold Time for a Write Access
Switching Characteristics
tCRL
ND_CE Setup Time to ARE Low
tCRH
ND_CE Hold Time From ARE High
tRP1
ARE Low to ARE High
tRHRL
ARE High to ARE Low
tRC1
ARE Low to ARE Low
Timing Requirements (ADSP-BF522/ADSP-BF524/ADSP-BF526)
tDRS
Data Setup Time for a Read Transaction
tDRH
Data Hold Time for a Read Transaction
Timing Requirements (ADSP-BF523/ADSP-BF525/ADSP-BF527)
tDRS
Data Setup Time for a Read Transaction
tDRH
Data Hold Time for a Read Transaction
Write Followed by Read
Switching Characteristic
tWHRL
AWE High to ARE Low
1 WR_DLY and RD_DLY are defined in the NFC_CTL register.
VDDEXT
1.8 V Nominal
Min
VDDEXT
2.5 V or 3.3 V Nominal
Min
Unit
1.0 × tSCLK – 4
1.0 × tSCLK – 4
ns
3.0 × tSCLK – 4
3.0 × tSCLK – 4
ns
0.0
0.0
ns
2.5 × tSCLK – 4
2.5 × tSCLK – 4
ns
0.0
0.0
ns
2.5 × tSCLK – 4
2.5 × tSCLK – 4
ns
(WR_DLY +1.0) × tSCLK – 4 (WR_DLY +1.0) × tSCLK – 4 ns
4.0 × tSCLK – 4
4.0 × tSCLK – 4
ns
(WR_DLY +5.0) × tSCLK – 4 (WR_DLY +5.0) × tSCLK – 4 ns
(WR_DLY +1.5) × tSCLK – 4 (WR_DLY +1.5) × tSCLK – 4 ns
2.5 × tSCLK – 4
2.5 × tSCLK – 4
ns
1.0 × tSCLK – 4
1.0 × tSCLK – 4
ns
3.0 × tSCLK – 4
3.0 × tSCLK – 4
ns
(RD_DLY +1.0) × tSCLK – 4 (RD_DLY +1.0) × tSCLK – 4 ns
4.0 × tSCLK – 4
4.0 × tSCLK – 4
ns
(RD_DLY +5.0) × tSCLK – 4 (RD_DLY +5.0) × tSCLK – 4 ns
14.0
10.0
ns
0.0
0.0
ns
11.0
8.0
ns
0.0
0.0
ns
5.0 × tSCLK – 4
5.0 × tSCLK – 4
ns
Rev. D | Page 43 of 88 | July 2013
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