ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
ND_CE
ND_CLE
ND_ALE
AWE
ND_D0-D7
tCWL
tCLEWL
tALEWL
tALH
tALEWL
tWP
tWHWL
tALH
tWP
tDWS
tWC
tDWH
tDWS tDWH
Figure 13. NAND Flash Controller Interface Timing - Address Write Cycle
tCWL
ND_CE
ND_CLE
ND_ALE
AWE
ARE
ND_D0-D7
tCLEWL
tALEWL
tWP
tWHWL
tWC
tDWS tDWH
tWP
tDWS
tDWH
Figure 14. NAND Flash Controller Interface Timing - Data Write Operation
Rev. PrG | Page 42 of 80 | February 2009