ADSP-BF526KBCZ-4X View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF526KBCZ-4X' PDF : 80 Pages View PDF
ADSP-BF522/523/524/525/526/527
Parallel Peripheral Interface Timing
Table 36 and Figure 19 on Page 46, Figure 23 on Page 50, and
Figure 25 on Page 51 describe parallel peripheral interface
operations.
Table 36. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW
PPI_CLK Width1
tPCLK
PPI_CLK Period1
Timing Requirements - GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
External Frame Sync Hold After PPI_CLK
tSDRPE
Receive Data Setup Before PPI_CLK
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
1 PPI_CLK frequency cannot exceed fSCLK/2
Preliminary Technical Data
ADSP-BF522/524/526
VDDEXT =
1.8 V
VDDEXT =
2.5/3.3 V
Min Max Min Max
ADSP-BF523/525/527
VDDEXT =
1.8 V
VDDEXT =
2.5/3.3 V
Min Max Min Max Unit
6.4
6.4
6.0
6.0
ns
25.0
25.0
15.0
15.0
ns
6.7
6.7
6.7
6.7
ns
1.0
1.0
1.0
1.0
ns
3.5
3.5
3.5
3.5
ns
1.5
1.5
1.6
1.5
ns
8.8
8.8
8.0
8.0 ns
1.7
1.7
1.7
1.7
ns
8.8
8.8
8.0
8.0 ns
1.8
1.8
1.8
1.8
ns
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
DATA0 IS
SAMPLED
DATA1 IS
SAMPLED
tSFSPE
tHFSPE
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
tSDRPE
tHDRPE
Figure 19. PPI GP Rx Mode with External Frame Sync Timing
Rev. PrG | Page 46 of 80 | February 2009
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