ADSP-BF534 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF534' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
These modes support ADC/DAC connections, as well as video
communication with hardware signalling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
DYNAMIC POWER MANAGEMENT
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
synchronous peripherals (SCLK). Asynchronous peripherals,
vide five operating modes, each with a different performance
such as the RTC, may still be running but cannot access internal
and power profile. In addition, dynamic power management
resources or external memory. This powered-down mode can
provides the control functions to dynamically alter the proces-
only be exited by assertion of the reset interrupt (RESET) or by
sor core supply voltage, further reducing power dissipation.
an asynchronous interrupt generated by the RTC. When in deep
Control of clocking to each of the peripherals also reduces
sleep mode, an RTC asynchronous interrupt causes the proces-
power consumption. See Table 4 for a summary of the power
sor to transition to the active mode. Assertion of RESET while
settings for each mode.
in deep sleep mode causes the processor to transition to the full-
Full-On Operating Mode—Maximum Performance
on mode.
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
Hibernate Operating Mode—Maximum Static Power
Savings
is the power-up default execution state in which maximum per-
The hibernate mode maximizes static power savings by dis-
formance can be achieved. The processor core and all enabled
abling the voltage and clocks to the processor core (CCLK) and
peripherals run at full speed.
to all of the synchronous peripherals (SCLK). The internal volt-
Active Operating Mode—Moderate Power Savings
age regulator for the processor can be shut off by writing b#00 to
the FREQ bits of the VR_CTL register. This disables both CCLK
In the active mode, the PLL is enabled but bypassed. Because the
and SCLK. Furthermore, it sets the internal power supply volt-
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
age (VDDINT) to 0 V to provide the greatest power savings. To
preserve the processor state, prior to removing power, any criti-
mode, the CLKIN to CCLK multiplier ratio can be changed,
cal information stored internally (memory contents, register
although the changes are not realized until the full-on mode is
contents, etc.) must be written to a non volatile storage device.
entered. DMA access is available to appropriately configured
L1 memories.
Since VDDEXT is still supplied in this mode, all of the external pins
three-state, unless otherwise specified. This allows other devices
In the active mode, it is possible to disable the PLL through the
that are connected to the processor to still have power applied
PLL control register (PLL_CTL). If disabled, the PLL must be
without drawing unwanted current.
re-enabled before transitioning to the full-on or sleep modes.
The Ethernet or CAN modules can wake up the internal supply
Table 4. Power Settings
regulator. The regulator can also be woken up by a real-time
clock wakeup event or by asserting the RESET pin, both of
Core
System Internal which initiate the hardware reset sequence.
PLL
Clock Clock Power With the exception of the VR_CTL and the RTC registers, all
Mode
PLL
Bypassed (CCLK) (SCLK) (VDDINT) internal registers and memories lose their content in the hiber-
Full On
Active
Sleep
Enabled No
Enabled/ Yes
Disabled
Enabled —
Enabled Enabled On
Enabled Enabled On
Disabled Enabled On
nate state. State variables may be held in external SRAM or
SDRAM. The CKELOW bit in the VR_CTL register controls
whether SDRAM operates in self-refresh mode which allows it
to retain its content while the processor is in reset.
Deep Sleep Disabled —
Disabled Disabled On
Power Savings
Hibernate Disabled —
Disabled Disabled Off
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wakeup causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
As shown in Table 5, the processors support three different
power domains which maximizes flexibility, while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
Rev. B | Page 13 of 68 | July 2006
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