ADSP-BF534 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF534' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
PIN DESCRIPTIONS
ADSP-BF534/ADSP-BF536/ADSP-BF537 processor’s pin defi-
nitions are listed in Table 9. In order to maintain maximum
function and reduce package size and pin count, some pins have
dual, multiplexed functions. In cases where pin function is
reconfigurable, the default state is shown in plain text, while the
alternate function is shown in italics. Pins shown with an aster-
isk after their name (*) offer high source/high sink current
capabilities.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface and the
buffered XTAL output pin (CLKBUF). On the external memory
interface, the control and address lines are driven high during
reset unless the BR pin is asserted.
All I/O pins have their input buffers disabled with the exception
of the pins noted in the data sheet that need pull-ups or pull-
downs if unused.
The SDA (serial data) and SCL (serial clock) pins are open drain
and therefore require a pull-up resistor. Consult version 2.1 of
the I2C specification for the proper resistor value.
Table 9. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
Type Function
Driver
Type1
O Address Bus for Async Access
A
I/O Data Bus for Async/Sync Access
A
O Byte Enables/Data Masks for Async/Sync Access A
I Bus Request
BG
O Bus Grant
A
BGH
O Bus Grant Hang
A
Asynchronous Memory Control
AMS3–0
O Bank Select
A
ARDY
I Hardware Ready Control
AOE
O Output Enable
A
ARE
O Read Enable
A
AWE
O Write Enable
A
Synchronous Memory Control
SRAS
O Row Address Strobe
A
SCAS
O Column Address Strobe
A
SWE
O Write Enable
A
SCKE
O Clock Enable
A
CLKOUT
O Clock Output
B
SA10
O A10 Pin
A
SMS
O Bank Select
A
Pull-Up/Pull-Down
This pin should be pulled high when
not used
Rev. B | Page 19 of 68 | July 2006
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