ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF537BBCZ-5AV' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 50). Figure 51 through Figure 60 on
Page 55 show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
VLOAD
50Ω
70Ω
50Ω
4pF
2pF
400Ω
TESTER PIN ELECTRONICS
45Ω
0.5pF
T1
DUT
OUTPUT
ZO = 50Ω (impedance)
TD = 4.04 ± 1.18 ns
14
12
RISE TIME
10
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 51. Typical Output Delay or Hold for Driver A at VDDEXT Min
12
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 50. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 52. Typical Output Delay or Hold for Driver A at VDDEXT Max
Rev. J | Page 53 of 68 | February 2014
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