ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 60 Pages View PDF
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Asynchronous Memory Read Cycle Timing
Table 16 and Table 17 on Page 26 and Figure 11 and Figure 12
on Page 26 describe asynchronous memory read cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 16. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
tDO
Output Delay After CLKOUT1
tHO
Output Hold After CLKOUT1
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
Min
Max
Unit
2.1
ns
0.8
ns
TBD
ns
TBD
ns
6.0
ns
0.8
ns
CLKOUT
AMSx
SETUP
2 CYCLES
tDO
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
tHO
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA15–0
BE, ADDRESS
tDO
tSARDY
tHARDY
tHO
tHARDY
tSARDY
tSDAT
READ
Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
tHDAT
Rev. PrD | Page 25 of 56 | May 2006
Share Link: 
